| 摘要 |
In some embodiments, the invention includes a domino gate including a domino stage node and an evaluate network. The evaluate network includes a first group of transistors coupled between the domino stage node and a voltage reference node. The gate also includes a second group of transistors coupled between respective ones of inputs of the first group of transistors and the voltage reference node. The gate may be a precharge domino gate or a predischarge domino gate. The gate may comprise a pull-up transistor coupled to the domino stage node, the pull-up transistor including an input to receive a clock signal (Clk) and wherein the second group of transistors have inputs to receive a clock signal (Clk*), which is an inverse of Clk. Clk may lead or trial Clk*.
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