发明名称 |
High-speed synchronous semiconductor memory having multi-stage pipeline structure and operating method |
摘要 |
In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.
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申请公布号 |
US2002048196(A1) |
申请公布日期 |
2002.04.25 |
申请号 |
US20010957821 |
申请日期 |
2001.09.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KWON KOOK-HWAN;SUH YOUNG-HO |
分类号 |
G11C11/417;G11C7/10;G11C11/413;(IPC1-7):G11C7/00;G11C5/00 |
主分类号 |
G11C11/417 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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