发明名称 |
Arrangement for testing integrated circuits |
摘要 |
The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.
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申请公布号 |
US2002047723(A1) |
申请公布日期 |
2002.04.25 |
申请号 |
US20010932086 |
申请日期 |
2001.08.17 |
申请人 |
FARKAS GEORG;GAPPISCH STEFFEN |
发明人 |
FARKAS GEORG;GAPPISCH STEFFEN |
分类号 |
G01R31/28;G01R31/3181;G01R31/3183;G01R31/3185;G01R31/319;H01L21/822;H01L27/04;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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