| 摘要 |
<p>The invention provides a PLL circuit (10) wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit (10) includes a phase detection circuit (11) and a frequency detection circuit (12). The frequency detection circuit (12) includes a pair of D-type flip-flops (124, 125) for sampling first and second clock signals (ICLK, QCLK) having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit (126) for logically operating the signals sampled by the D-type flip-flops (124, 125) and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit (126) generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation. <IMAGE></p> |
