| 摘要 |
PURPOSE: A method for fabricating a semiconductor device is provided to reduce parasitic capacitance between upper poly plugs of a bit line and a capacitor, by forming a sufficiently thick sidewall of a bit line insulation layer. CONSTITUTION: An isolation region is formed in a semiconductor substrate(31) to define an active region. A plurality of word lines are formed on the semiconductor substrate. A sidewall of a word line insulation layer is formed on both side surfaces of the word line. A lower plug connected to the semiconductor substrate in the active region is formed. An insulation layer is deposited and planarized on the semiconductor substrate. An interlayer dielectric(37) is deposited on the semiconductor substrate, and a bit line contact is so formed that a part of the lower plug is exposed. A plurality of bit lines(42) are formed on the semiconductor substrate. The first and second insulation layers are deposited, and are selectively removed to form the first and second bit line insulation layer sidewalls(43a,44a) on both side surfaces of the bit line while the surface of a lower poly plug(35) is exposed. The third insulation layer is deposited, and is selectively eliminated to form the third bit line insulation layer sidewall(45) on both side surfaces of the bit line. A native oxide layer generated in the exposed lower plug is removed. Polysilicon is deposited, and is planarized to form an upper poly plug(46) electrically connected to the lower poly plug through the bit line contact.
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