Reliable polycide gate stack with reduced sheet resistance and thickness

摘要

Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.