发明名称 |
Testing method for buried strap and deep trench leakage current |
摘要 |
A method for measuring both buried strap and deep trench leakage currents in DRAM cell capacitors. By keeping the voltages on both plates of the capacitor equal, the buried strap leakage current (IBS) may be isolated and measured. A range of voltages is applied to a terminal of an associated transistor to obtain a corresponding range of buried strap leakage currents. An unequal voltage is next applied across the capacitor, and a total leakage current is measured. By applying a known potential to a substrate of the transistor during this total leakage current measurement, the associated IBS may be determined. Next, the IBS is subtracted from the measured total leakage current to obtain the deep trench leakage current (IDT).
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申请公布号 |
US6377067(B1) |
申请公布日期 |
2002.04.23 |
申请号 |
US20000495753 |
申请日期 |
2000.02.01 |
申请人 |
WINBOND ELECTRONICS CORPORATION |
发明人 |
YANG SHIH-HSIEN;CHAO CHUAN-JANE |
分类号 |
G01R31/26;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/26 |
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