| 摘要 |
A semiconductor test system for efficiently testing a semiconductor device (DUT) having a phase lock loop (PLL) circuit therein. The semiconductor test system includes a first clock and waveform generator for supplying a clock signal to the PLL circuit at a start of the first pattern block, a second clock and waveform generator for supplying pattern data to the DUT during each of the pattern blocks, a pattern generator for generating pattern data, and a timing generator for generating a tester rate signal, a clear signal, and a gate signal for controlling the tester rate signal and the clear signal in the first and second clock and waveform generators. The clock signal is continuously provided to the PLL circuit until the end of the last pattern block while the pattern data to the data pin is reset between the end of the current pattern block and the start of the next pattern block.
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