| 摘要 |
PURPOSE: A memory architecture for buffering JPEG video data is provided to use a small-sized memory to simultaneously read and write 640 pixel times 480 line data without collision, so as to enable a system-on-chip by a small-sized semiconductor chip with a JPEG image compression engine. CONSTITUTION: A video input buffer memory(22) is composed of four memories. A memory controller(13) comprises as follows. An index counter 'i' counts numbers from 0 to 7 in order. An index counter 'j' counts numbers from 0 to 7 in order. An index counter 'k' counts numbers from 0 to 79 in order. An index counter 'n' counts a value of 0 or 1. An index counter 'ITER' counts a value of 0 or 1. An index counter 'jj' counts a value of 0 or 4. An index counter 'm' counts numbers from 0 to 15 in order. An index counter 'T' counts numbers from a range of 0 to 4 in order. A counter 'P' counts numbers from a range of 0 to 3. An operation circuit selects one of the four memories to calculate memory IDs and memory addresses when writing video data in the four memories. The memory IDs are calculated from a formula '(i + j + k)%4. An operation circuit sets n=0 in correspondence with Y data of the video data, and sets n=1 in correspondence with UV data. If the counter 'ITER' is equal to 0, the operation circuit calculates addresses of the video data from a formula '(k x 32 + n x 16 + j x 2 + i/4). If the counter 'ITER' is equal to 1, the operation circuit calculates the addresses from a formula '(k x 32 + n x 16 + i x 2 + j/4). |
