发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit capable of quickening a lockup time in an arbitrary set time while ensuring high C/N characteristics. SOLUTION: The current value Icp [A] of an output current signal Icp of a charge pump circuit 2 is switched synchronously with a timer signal flosw outputted by a fast lock timer circuit 7 within a set time set based on frequency- division rate setting data inputted form the outside part. In this case, when a timer signal flosw outputted from the fast lock timer circuit 7 is a high level, current quantity Icp [A] to be supplied to a low pass filter 3 is set so as to be a large value so that high speed lockup can be attained, and when the timer signal flosw outputted from the fast lock timer circuit 7 is a low level, the current quantity Icp [A] to be supplied to the low pass filter 3 is set so as to be a small value so that C/N can be improved.
申请公布号 JP2002118461(A) 申请公布日期 2002.04.19
申请号 JP20000311730 申请日期 2000.10.05
申请人 NEC YAMAGATA LTD 发明人 ICHIMURA ATSUHIKO
分类号 H03L7/08;H03L7/089;H03L7/093;H03L7/107;H03L7/18;H04L7/033 主分类号 H03L7/08
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