| 摘要 |
PROBLEM TO BE SOLVED: To improve execution timing of a level balance between pairs of digit lines which carry out data-write surely. SOLUTION: This device is provided with a balance means, which sets a potential of the pairs of digit lines to an intermediate potential VCC/2 level of a power source potential VCC between pairs of digit lines connecting a bus connection switching section (YSW) 14, inserted between pairs of digit lines Dj (j=1 to n), DjB (j=1 to n) and pairs of data transfer bus lines I/OT, I/ON and a sense amplifier 12. The balance means has a constitution, in which balance operation is controlled by a balance-selecting means 17j (j=1 to n) for performing logical synthesis of a column address strobe(CAS) signal, its delay signalΦcdly and a decoding signal of a column address which specifies the column address.
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