| 摘要 |
PROBLEM TO BE SOLVED: To design an LSI logic circuit having high-frequency operation in a short period by providing a high-speed arranging means which has a short processing time, securing the same design quality as that obtained by arrangement design in a downstream process, and preventing an arrangement result assumed at logic generation time from fluctuating as the design change. SOLUTION: A hardware description language as an input is mapped into cell components, logic clusters as partial circuits are generated from the mapping result, and detailed logic circuits are generated for each cluster; and the arrangement positions of the logic clusters are determined and it is decided whether or not a target operation frequency is achieved by using the result. When the degree of violence of delay is small as a result of the decision making, a return to the generation of a detailed logic circuit is made and when the degree of violence of delay is large, a return to the hardware description is made to redesign a logic circuit. The logic clusters are integrated when the relation between the number of gates and the number of ports is improved.
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