| 摘要 |
PROBLEM TO BE SOLVED: To reduce access latency to a cache tag memory and to reduce latency required for the transaction processing of a computer system. SOLUTION: A cache tag buffer 270 for storing a part of the cache tag memory 26 is prepared. When a memory processing request is issued from a processor 10, a cache control circuit 280 retrieves both of the cache tag memory 260 and the cache tag buffer 270, and in the case that a target cache block is present in the cache tag buffer 270, a cache data memory 250 is accessed by using the information of the cache block without waiting for the retrieved result of the cache tag memory 260.
|
