发明名称 METHOD OF GENERATING TEST PATTERN FOR INTEGRATED CIRCUIT
摘要 A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.
申请公布号 US2002046376(A1) 申请公布日期 2002.04.18
申请号 US19990265346 申请日期 1999.03.09
申请人 YAMAUCHI HISASHI 发明人 YAMAUCHI HISASHI
分类号 G01R31/28;G01R31/3183;G01R31/3185;(IPC1-7):G01R31/28;G06F11/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址