| 摘要 |
<p>A hardware Java Accelerator (42) is comprised of a decode stage (26b) and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer (82) is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator (42) need not be flushed upon an interrupt. A native PC monitor (54) is also used. While the native PC (54) is within a specific range, the hardware accelerator is enabled to convert the Java bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU (25) operates on naive instructions obtained from the memory.</p> |
