| 摘要 |
An interface (200) between a frame memory (110) and a display processing system (120) is provided wherein the number of bits-per-pixel is continuously programmable to any integer value between 1 and an upper limit, nominally 32 bits-per-pixel, without regard to the underlying structure of the processors that provide or use the pixel data. Data is read from memory (110) in fixed increments, based on the underlying structure of the processor, thereby providing an efficient interface with conventional processing systems, and subsequently processed based on the programmed number of bits-per-pixel. The architecture also allows for a programmable order of bits and components within each pixel to provide a programmable interface with other devices and components within a graphics or video processing system. Each component of the pixel format is allocated to one of a number of channels, nominally four, for subsequent processing and rendering to a display system.
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