| 摘要 |
The present invention discloses a memory testing apparatus. The testing apparatus can be embedded on a chip with embedded memory block or a memory chip to reduce the testing time of memory blocks or memory devices. Through the selection of testing modes and the data processing of the processing device, the correctness of the output data of a memory block can be represent with the data state of a verifying data. The data output can be pre-processed and simplified as the verifying data to reduce the test time. The apparatus for testing memories includes a memory block, a processing device, and a mode selecting device. An output data is read out from the memory block. The processing device is employed for processing the output data to generate a verifying data. The verifying data has a bit number less than a that of the output data. The mode selecting device is utilized for selecting testing modes of the processing device. In the case, the testing modes includes an all-high mode, an all-low mode, a data pattern verifying mode, and a by-pass mode.
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