发明名称 Flat display panel having internal lower supply circuit for reducing power consumption
摘要 A flat display employs at least one high voltage different from logic voltages. The display has a voltage detection unit and a drive control signal control unit. The voltage detection unit is used to detect the high voltage. The drive control signal control unit is used to control drive control signals of the flat display in accordance with the detected high voltage. This arrangement eliminates charging currents that are applied to a display panel but have nothing to do on the actual displaying of data, or reactive currents due to unnecessary switching operations, thereby reducing power consumption.
申请公布号 US2002044145(A1) 申请公布日期 2002.04.18
申请号 US20010974806 申请日期 2001.10.12
申请人 FUJITSU LIMITED OF KAWASAKI 发明人 TOMIO SHIGETOSHI;MATSUI NAOKI;YAO SHINPEI
分类号 G06G5/00;G09G3/20;G09G3/28;G09G3/288;(IPC1-7):G09G5/00 主分类号 G06G5/00
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