Schaltung zum Beschränken von Mehrfachzugriffen für eine Mehrfachspeichereinrichtung

摘要

The memory access limiting circuit detects when two or more of memory units (NVM1-3) associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit (15). The integrated circuit also includes an address decoding (28) for receiving the unique address signal (A5) and causing a write enable signal to be generated for the memory units (NVM1-3) and one of a plurality of chip select signals to be generated for a respective one (NVM3) of the pins (P6-P8) of the memory units (NVM1-3). The monitoring circuit monitors the levels of the integrated circuit assigned for selecting the respective memory unit (NVM3). The monitoring circuit (438, 440, 442, 444) generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor (13) for corrective action.