发明名称 |
Methods of planarizing insulating layers on regions having different etching rates |
摘要 |
An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.
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申请公布号 |
US2002045337(A1) |
申请公布日期 |
2002.04.18 |
申请号 |
US20010917601 |
申请日期 |
2001.07.27 |
申请人 |
NAM GEE-WON;PARK GI-JONG;HWANG HONG-KYU;BAE JUN-SHIK;PARK YOUNG-RAE;KIM JUNG-YUP;YOON BO-UN;HAH SANG-ROK |
发明人 |
NAM GEE-WON;PARK GI-JONG;HWANG HONG-KYU;BAE JUN-SHIK;PARK YOUNG-RAE;KIM JUNG-YUP;YOON BO-UN;HAH SANG-ROK |
分类号 |
H01L21/302;H01L21/3105;H01L21/311;H01L21/44;H01L21/461;H01L21/4763;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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