发明名称 ADAPTIVE SYNCHRONIZATION MECHANISM FOR DIGITAL VIDEO DECODER
摘要 <p>An adaptive clocking mechanism is provided for a digital display system. The digital display system includes a clock recovery system, for recovering a system, for recovering a system time clock from a video bit-stream generated at an encoder, and a decoding system for decoding an decompressing the video bit-stream at a frame rate. The adaptive clocking mechanism operates to determine, from video format information transmitted from the encoder, the occurrence of a frame rate at which a transmitted signal is encoded that differs from a frame rate expected by the decoder. Upon such a determination, the adaptive clocking mechanism further operates to select a modifier (22) from a group of modifiers based on format information derived from the video bit-stream, including the encoded frame rate. The selected modifier is ten applied to a synchronisation function of the decoder in a manner to bring the decoder operation into synchronisation with the non-expected encoder frame rate.</p>
申请公布号 WO0232116(A1) 申请公布日期 2002.04.18
申请号 WO2000US28057 申请日期 2000.10.11
申请人 SONY ELECTRONICS INC. 发明人 OTA, TAKAAKI
分类号 H04N5/04;H04N5/44;H04N5/46;(IPC1-7):H04N5/04 主分类号 H04N5/04
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