发明名称 Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
摘要 A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3~5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells.
申请公布号 US2002045319(A1) 申请公布日期 2002.04.18
申请号 US20010839966 申请日期 2001.04.23
申请人 HALO LSI DEVICE & DESIGN TECHNOLOGY INC. 发明人 OGURA SEIKI;HAYASHI YUTAKA;OGURA TOMOKO
分类号 G11C11/56;G11C16/04;H01L21/8246;H01L27/115;(IPC1-7):H01L21/336 主分类号 G11C11/56
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