发明名称 METHOD FOR FABRICATING WAFER LEVEL CHIP-SIZE-PACKAGE
摘要 PURPOSE: A method for fabricating a wafer level chip-size-package(CSP) is provided to form an elastomer layer of a uniform thickness on a wafer, by laminating an elastomer layer on the wafer wherein a metal plate is attached to the upper surface of the elastomer layer. CONSTITUTION: A semiconductor device and a pad are fabricated on the wafer(20), and a bump is formed on the pad. The metal plate is attached to the upper surface of the elastomer layer(22a) having the same type as the wafer. A penetration hole(23) is formed in the elastomer layer to which the metal plate located in a position corresponding to the position of the pad on the wafer is attached. The metal plate is patterned to form a metal interconnection(22c). A solder resist layer(24) is formed on the metal interconnection and the elastomer layer. The solder resist layer is partially eliminated to expose a part of the upper surface of the metal interconnection. The elastomer layer to which the metal plate is attached is laminated on the wafer so that the bump on the wafer is inserted into the penetration hole. A conductive ball(25) is attached to the upper surface of the exposed metal interconnection.
申请公布号 KR20020028467(A) 申请公布日期 2002.04.17
申请号 KR20000059490 申请日期 2000.10.10
申请人 LIM, KWAN IL 发明人 LIM, KWAN IL
分类号 H01L23/12;(IPC1-7):H01L23/12 主分类号 H01L23/12
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