| 摘要 |
<p>A bus control apparatus for interconnecting a plurality of bus lines to which a central processing apparatus (1) and a plurality of different peripheral equipments (7,8) are connected, comprising:
a main bus (9) to which at least said central processing unit (1) is connected;
a sub bus (10) to which said plurality of different peripheral equipments (7,8) are connected;
storage means (14) for storing a bus width and an addressing type information of said plurality of different peripheral equipments (7,8), said addressing type information indicating whether a respective peripheral equipment (7,8) uses fixed or variable addressing, and
a single controller (16) for controlling reading of data from and writing of data to said respective peripheral equipment (7,8) in accordance with the respective bus width and the respective addressing type of said respective peripheral equipment (7,8) stored in said storage means (14).</p> |
