发明名称 |
Method for accessing memory |
摘要 |
<p>A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types. <IMAGE></p> |
申请公布号 |
EP1197867(A2) |
申请公布日期 |
2002.04.17 |
申请号 |
EP20010129841 |
申请日期 |
1997.05.28 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
MCINTYRE, KENNETH L. JR.;LINDQUIST, STEVEN P.;REIPOLD, ANTHONY M.;COLLINS, COLLEEN M.;PECHONIS, DANIEL W.;WINTER, ROBERT L. |
分类号 |
G06F12/02;G06F12/08;G06F13/16;G06F13/42;(IPC1-7):G06F12/02 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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