PROCESS FOR FETCHING OUT ERROR STATISTICS DATA

摘要

For implementing the method for reading error statistics data, a hardware configuration has processing units (CTR0, CTR1) that operated in microsynchronous parallel operation for the processing of ATM information. The processing units are connected at the ATM end to a switching matrix (SN0, SN1) and via a bus interface (B-I) to a central processor. The central processor is used for evaluating error statistics arising in the processing units and for monitoring the synchronous operation by comparing the processing results. The error statistics data is packed into ATM transmitter cells and looped back via the switching matrix in each case to both processing units and then supplied to the central processor via the bus interface. This prevents the erroneous indication of the loss of microsynchronism when error statistics for the two processing units differ.