| 摘要 |
PURPOSE: A PCI bus controller that has HPI of DSP and DMA interface is provided to support an HPI function and a DMA function, which has high-speed transmission, by allocating one channel of EMIF of DSP to PCI controller, FPGA. CONSTITUTION: A target controller(10) processes a resource usage request from a system board or PnP commands, and communicates with HPI of DSP through a target backend controller(20). A master controller(30) sends DMA data from EMIF of DSP to the host. A parity generator(50) sends the data with even parity. In transmission between DSP and the host, the control of DSP through HPI is a slave mode transmission and high capacity transmission through EMIF is a master mode transmission. DSP supports HPI and DMA function, which has high-speed transmission, by allocating one channel of EMIF of DSP to PCI controller, FPGA.
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