| 摘要 |
A priority determining circuit for a non-volatile memory formed by at least one pair of memory banks, each bank having a counter, including a circuit for latching a read address of the memory; a master latch circuit for the address; a slave latch circuit for the address; a pointer circuit for read paths of the memory bank to be read of the memory, stimulated by the master latch circuit; a circuit for enabling a path for connecting the master latch circuit and the slave latch circuit; a circuit for enabling a path for connecting the slave latch circuit and the master latch circuit; a circuit for managing the increment of the counters which is connected to the slave latch circuit; the read address of the memory being loaded by the master latch circuit into the slave latch circuit and then by the slave latch circuit into the master latch circuit alternately, the master latch circuit synchronizing a timer circuit of the memory which is meant to activate sense amplifiers of the memory and the slave latch circuit driving the circuit for managing the increment of the counters, for an advancement of the read cycle of the memory.
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