| 摘要 |
A semiconductor device, such as a SDRAM, having internal signals (FICLK and ICLK) generated with similar timings with respect to each other, even when operating at a frequency that is too low for proper operation of a synchronous circuit (103). According to one embodiment, the semiconductor device may include an internal signal generator (100) having a first stage circuit (101), timing control circuit (110) and synchronous circuit (103). The first stage circuit (101) may receive an external CLK and generate an internal signal ICLK'. The timing control circuit (110) may be coupled to receive internal signal ICLK' and generate internal signal ICLK'. The synchronous circuit (103) may be coupled to receive internal signal ICLK' and generate internal signal FICLK. Internal signals (FICLK and ICLK) may have a timing with respect to one another in a normal mode of operation. When operating at a frequency too low for a synchronous circuit (103), internal signal generator (100) may include a test mode of operation in which timing control circuit (110) allows internal signals (FICLK and ICLK) to have similar timings with respect to one another in the test mode as in a normal mode of operation.
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