发明名称 Fault tolerant computing system using instruction counting
摘要 In order to provide a microprocessor based fault tolerant computing system, hardware counters or event monitors that are normally included on the microprocessor chips are used to count application instructions that are being executed by the microprocessors. By counting the instructions and preempting the execution of the application program after a predetermined number of instructions have been executed, it is possible to cause the application programs to execute in congruent frames so that results from the application can be checked at congruent points of their execution. If the results do not match, then the program can be terminated or if a number of microprocessors are being used, the results can be voted on and the ones that match can be used in further computation by the system.
申请公布号 US6374364(B1) 申请公布日期 2002.04.16
申请号 US19990234797 申请日期 1999.01.19
申请人 HONEYWELL INTERNATIONAL, INC. 发明人 MCELROY JAMES J.;JOHNSON CLARK
分类号 G06F11/00;G06F11/16;G06F11/18;(IPC1-7):G06F11/00 主分类号 G06F11/00
代理机构 代理人
主权项
地址