| 摘要 |
In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.
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