发明名称 Clock-delayed pseudo-NMOS domino logic
摘要 A logic gate includes a logic circuit having an input node and an output node, an enabling transistor coupled between a first power supply node and the output node, the enabling transistor adapted to couple the output node to the first power supply node during an evaluation phase in the logic gate, and a pre-charge transistor coupled between the output node and a second power supply node, the pre-charge transistor adapted to couple the output node to the second power supply node during a pre-charge phase in the logic gate.
申请公布号 US6373290(B1) 申请公布日期 2002.04.16
申请号 US20000651630 申请日期 2000.08.30
申请人 MICRON TECHNOLOGY, INC. 发明人 FORBES LEONARD
分类号 H03K19/096;(IPC1-7):H03K19/096 主分类号 H03K19/096
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