发明名称 Lateral bipolar junction transistor with reduced parasitic current loss
摘要 A semiconductor process is disclosed which forms openings in a dielectric layer through which the emitter region and collector region of lateral bipolar junction transistors are formed. In one embodiment of the invention, the emitter openings for the lateral bipolar junction transistors are first protected by a photoresist layer that is patterned to expose the collector openings for the transistors. A first implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the emitter openings, and a second implant is performed, this time into both the collector and the emitter regions, and then diffused to a suitable depth that is shallower than the first implant (used in the collector). Since the two implants are aligned to openings through the dielectric layer defined typically by a single mask, excellent base-width control and repeatability is achieved for the lateral transistors. Through careful selection of the collector and emitter diffusion profiles (i.e., depth and concentration), a more optimal PNP transistor may be constructed that has a collector deeper than its emitter. This scheme provides far greater collection efficiency than a traditional lateral PNP transistor made of the same diffusion for both the emitter and the collector. Greater collection efficiency provides improved Beta, better gain matching, and less parasitic loss of injected holes to a surrounding P-type junction isolation.
申请公布号 US6372595(B1) 申请公布日期 2002.04.16
申请号 US20000563979 申请日期 2000.05.03
申请人 LEGERITY, INC. 发明人 THIEL FRANK L.;MOORE WILLIAM E.;WEBB BRUCE
分类号 H01L21/331;H01L29/735;(IPC1-7):H01L21/331 主分类号 H01L21/331
代理机构 代理人
主权项
地址