| 摘要 |
There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper side 20 bits [31:12] of the base address match the base address stored in a upper side address storage section in CAM 35, and upper side 4 bits [15:12] of the offset address match the offset address stored in the CAM; a comparator for judging whether or not a carry signal outputted from the adder and a carry signal stored in a carry storage section in the CAM are matched; and a match detector for outputting a match signal when comparison results of the comparators are matched. With lower side 12 bits of the virtual address, the judgment of match/mismatch is performed only with the carry signal. Therefore, the match/mismatch of the virtual address can be judged before the addition processing in the adder is completed.
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