| 摘要 |
A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 mum or less in depth) of source/drain regions of a MOSFET with a double drain structure. In the step (a), a gate electrode is formed over a main surface of a single-crystal Si substrate of a first conductivity type through a gate insulating film. In the step (b), a dopant of a second conductivity type is ion-implanted into the substrate at an acceleration energy of 1 keV or lower under a condition that the amount of point defects induced in this step (b) is minimized or decreased, thereby forming first and second doped regions of the second conductivity type. In the step (c), a pair of sidewalls spacers are formed. In the step (d), a dopant of the second conductivity type is ion-implanted into the substrate, thereby forming third and fourth doped regions of the second conductivity type having a depth greater than the first and second doped regions and a lower dopant concentration than the first and second doped regions to be overlapped therewith. In the step (e), the substrate is subjected to an annealing process, thereby constituting one of a pair of source/drain regions with a double drain structure by the first and third doped regions and the other thereof by the second and fourth doped regions.
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