发明名称 Memory that stores multiple bits per storage cell
摘要 A multi-level memory in which each storage cell stores multiple bits. The memory includes a plurality of storage words, a data line, a plurality of reference lines, and a read circuit. Each storage word includes a data memory cell and a plurality of reference memory cells. A stored charge determines a conductivity value measurable between the first and second terminals of each memory cell. The read circuit generates a digital value indicative of the value stored in the data memory cell of a storage word that is connected to the data and reference lines by comparing the conductivity of the data line with a continuous conductivity curve determined by the conductivities of the reference lines.
申请公布号 US6373767(B1) 申请公布日期 2002.04.16
申请号 US20000689496 申请日期 2000.10.11
申请人 PATTI ROBERT 发明人 PATTI ROBERT
分类号 G11C11/4099;G11C11/56;G11C16/04;G11C16/10;G11C16/28;G11C27/00;(IPC1-7):G11C7/02 主分类号 G11C11/4099
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