| 摘要 |
PURPOSE: A direct digital frequency synthesizer is provided, which reduces a size of a chip by reducing a size of a lookup table without performance degradation, and makes it easy to make a one-chip with a peripheral chip. CONSTITUTION: An adder(100) adds a frequency control word(FCW) and a correction value(FTL) by a frequency correction algorithm, and a phase accumulator(110) accumulates an output of the adder in response to a clock(clk) and outputs the accumulated value to an address synchronized to the clock. A complementer(120) makes 2's complement of the address from the phase accumulator. A multiplexer(130) outputs the address from the phase accumulator or the address complemented through the complementer selectively. Lookup tables(140,150) stores data of sine and cosine corresponding to a quarter of pi. An exclusive OR gate(220) performs an exclusive OR operation of MSB2 and MSB3 of the address from the phase accumulator, and a multiplexer(160) outputs a sine data or a cosine data selectively from the lookup tables. A complementer(180) makes 2's complement of sine or cosine data from the multiplexer. A multiplexer(200) outputs data from the multiplexer(160) or data from the complementer as a sine signal.
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