发明名称 FLEXIBLE FEHLERKORREKTURCODE/PARITÄTSBIT- ARCHITEKTUR
摘要 A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal. <IMAGE>
申请公布号 AT216096(T) 申请公布日期 2002.04.15
申请号 AT19950101257T 申请日期 1995.01.30
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 KIEHL, OLIVER
分类号 G11C11/413;G06F11/10;G11C11/401;G11C29/00;G11C29/42;(IPC1-7):G06F11/10 主分类号 G11C11/413
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