发明名称 SEMICONDUCTOR DEVICE, LAYOUT DEVICE, AND METHOD OF LAYOUT
摘要 PROBLEM TO BE SOLVED: To provide a layout method for making it possible to draw a reinforcement power wire easily to a main power wiring, in which a voltage drop is caused, even when a signal wiring and the like is already arranged. SOLUTION: A floor planning is carried out, and a logical element and an I/O are provided. A main power wiring between the arithmetic element and the I/O, a clock wiring, a signal wiring are provided. Before and after these locations, a voltage drop preventive element is provided at a position capable of locating the logical element, and a power feeding I/O is provided at a position capable of locating the I/O. In addition, the analysis of voltage drop in the main power wiring is carried out, and the reinforcement power wiring is provided between the voltage drop preventive element and the power feeding I/O when there is a drop in voltage.
申请公布号 JP2002110802(A) 申请公布日期 2002.04.12
申请号 JP20000295146 申请日期 2000.09.27
申请人 TOSHIBA CORP 发明人 ORITA HIROSHIGE
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/82 主分类号 G06F17/50
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