| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for a layout thereof, where a resistant value between a power line at a power potential connecting a function element with a capacitor and a ground line at a ground potential can be set as a desired value and a capacitor layout can be realized, without the need for investigating individually by the layout of a macro cell in the semiconductor. SOLUTION: The semiconductor device comprises a macro cell, including a function cell which is the function element with the capacitor and a macro cell including a function cell which is the function element without the capacitor. The function cell, which is the function element with the capacitor included in the macro cell, is defined as the driver cell of a minimum cell unit, comprises a function element 1 comprising an inverter, a function element 2 comprising a clocked inverter, a capacitor 3 or the like and is configured, by adding the capacitor between the power potential (VCCL) of the function elements 1, 2 in the function cell which is a minimum cell unit and the ground potential (VSSL).
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