| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which increases bus efficiency. SOLUTION: This system is equipped specially with a 1st chip signal input pin for receiving a 1st chip select signal for a row address strobe and a 2nd chip select signal input pin for receiving a 2nd chip select signal for a column address strobe. Further, the system is equipped specially with at least one row instruction input pin and one column instruction input pin. Furthermore, the system is equipped specially with multiple row address input pins and column address (half-size end) input pins. Specially, a row instruction and a column instruction are inputted in response to two successive chips, i.e., two edges. The 1st chip select signal and 2nd chip select signal, on the other hand, are generated by a memory controller and inputted to respective memory modules through mutually different bus lines. |
