发明名称 MUTE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a mute circuit capable of eliminating the need for an external DC power supply by generating a bias voltage inside of a semiconductor integrated circuit, thereby decreasing an external terminal. SOLUTION: The mute circuit supplies a predetermined negative voltage to the base of a muting MOS transistor M5 to turn off in response to switching of a switch 38 and outputs an input signal without damping by turning off the MOS transistor M5. Since the mute circuit has an oscillation circuit 44 for generating an oscillation signal and a clamping and smoothing circuit (C11, M2, R1 and C12) for obtaining the predetermined negative voltage by clamping and filtering the oscillation signal, the bias voltage of the predetermined negative voltage can be generated inside of the semiconductor integrated circuit, thereby eliminating the need of the external DC power supply and decreasing the external terminal of the semiconductor integrated circuit.
申请公布号 JP2002111446(A) 申请公布日期 2002.04.12
申请号 JP20000293009 申请日期 2000.09.26
申请人 MITSUMI ELECTRIC CO LTD 发明人 YAMASATO KEISUKE
分类号 H03F1/00;H03H11/24;(IPC1-7):H03H11/24 主分类号 H03F1/00
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