| 摘要 |
A PLL circuit is provided wherein it is possible not only to get a high C/N ratio characteristic but also to speed up lock-up time at arbitrary intervals. A current value Icp [Ampere] of an output current signal Icp outputted from a charge pump circuit is switched synchronizing with a timer signal flosw outputted from fast lock timer circuit within a set time set up on the basis of externally inputted dividing ratio setting data. Thereby, when the timer signal flosw outputted from the fast lock timer circuit is on a high level, it is possible to set up the current value Icp [Ampere] supplied to a low-pass filter to a larger current value and speed up the lock-up. On the other hand, when the timer signal flosw outputted from the fast lock timer circuit is on a low level, it is possible to get the current value Icp [Ampere] supplied to the low-pass filter under control to a small current value and get a high C/N ratio.
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