| 摘要 |
An improvement to a conventional multistage pipelined Analog-to-Digital Converter (ADC) 1 having multiple stages 11-14, connected one to the next by an interstage amplifier 113, 123, 133, each stage with a flash digital-to-analog converter (DAC) 111, 121, 131, a digital-to-analog converter (DAC) 112, 122, 132 producing an associated intermediate analog signal, a subtractor 113, 123, 133 of intermediate analog signals to produce an analog difference signal fed to the interstage amplifier of a next following stage, and a thermometer encoder 114, 124, 134 producing an associated digital output signal; the improvement directed to canceling noise resultant from component mismatch, particularly mismatched capacitors paired with a first-stage DAC 212 of the ADC 1. The improved ADC 2 uses in at least a first, and preferably two, stages 21, 22: (i) a flash DAC 212, 222 of a dynamic element matching (DEM) type producing, as well as an associated intermediate analog signal, random bits and parity bits; (ii) a Digital Noise Cancellation (DNC) logic circuit 217, 227, receiving the random bits and the parity bits and a digitized residue sum of the digital output signals arising from all stages beyond a stage of which the DNC logic circuit 217, 227 is a part, so as to produce an error estimate for the stage; and (iii) a subtractor 218, 228 subtracting the error estimates of the DNC logic circuits 217, 227 from the combined digital output signal of all higher stages 022-24 in order to produce a corrected ADC digital output signal. A14-bit 4-stage pipelined ADC 2 having, by way of example, a theoretical optimum conversion precision of 14.1 bits and a realistic conversion precision of 10.4 bits, is enhanced by modestly-sized and continuously-automatically-operative DNC to realize 13.3 bits conversion precision.
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