发明名称 Phase-locked loop circuit
摘要 In a PLL circuit comprising a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, one channel processing the useful signal components and the other channel processing the disturbance signal components of the synchronisation pulses. Each channel has two tracks, for generation of a potential difference, each track being connected to a capacitor plate.
申请公布号 US2002041651(A1) 申请公布日期 2002.04.11
申请号 US20010971748 申请日期 2001.10.04
申请人 ATMEL GERMANY GMBH 发明人 SCHWARZMUELLER MARCO
分类号 H03L7/089;H03L7/099;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03L7/089
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