A system and method that attempts to prevent address aliasing when using a single address cycle to transmit a target address in a computer system comprising target devices having addresses of different sizes. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The second address range includes addresses that are specified according to a first prescribed value for a most significant bit. The first address range includes addresses that are specified according to a second prescribed value for the most significant bit to exclude the second address range such that the initiator device can transmit the first address to the first target device without aliasing the second address with the first address. The initiator device selects either the first address range or the second address range for the target address by specifiying either the first prescribed value or the second prescribed value in the target address.
