| 摘要 |
<p>The present invention is a system and method that facilitates simplified debugging of internal component scan testing with minimal impacts to normal operations and manufacturing processes. In one embodiment of the present invention, a TAP controlled internal scan test intermediate debugging system includes an intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input pin, a scan test chain final output pin. The components of the intermediate TAP controlled internal scan test debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. The intermediate TAP controller internal scan test system transmits an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system utilizes an internal scan observe register to store information indicating which intermediate internal scan test chain signal to forward as a TAP TDO signal. By selectively transmitting intermediate internal scan test chain signals (ISS) off of the IC, manipulation by a design circuit block of a scan test vector value input is isolated in an analytical sense from manipulations of the test vector value by other design circuit blocks. One embodiment of the present invention also controls intermediate scan test input signals.</p> |
