| 摘要 |
<p>An address decoder for decoding a wobble signal to reproduce an address signal comprising a PLL circuit (103) for generating a PLL clock signal PCLK synchronous with an external clock signal CLK, a frequency divider (104) for dividing the frequency of the PLL clock signal PCLK, a selector (102) for selecting either a binary wobble signal ADRT or its inverted signal, a timing generator (106) for generating signals including an SYNCWIN1, an SYNCWIN2, a BENA, a CENA1, CENA2, a CPOLE, and an OUTENA, a bi-phase decoder (107) for decoding the wobble signal ADRLG selected by the selector (102), a gray code decoder (108) for decoding a bi-phase decoded data BDAT, and an output control circuit (110) for outputting the decoded address signal ADROUT.</p> |
