发明名称 CLOCK SUPPLY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a clock supply circuit which can supply clocks of different frequencies to respective processing circuits only by using an external oscillator of a low frequency and in which a circuit configuration can be simplified and low power consumption can be realized. SOLUTION: A multiplication circuit 120 multiplies a reference clock RCK and generates a multiplication clock signal CLK, a clock for reception generation circuit 130 performs frequency division of the multiplication clock signal CLK with a prescribed frequency division ratio and generates a clock signal CK1 having a desired constant frequency, a clock for DSP generation circuit 132 can supply the clock signal CK1 in which synchronization with a received signal is maintained and a clock signal CK2 whose frequency is variably controlled in accordance with a processing load, because the clock signal CK2 whose frequency can be varied in accordance with the processing load of a DSP with a frequency division ratio set in accordance with the decision results of a load decision circuit 210.
申请公布号 JP2002108490(A) 申请公布日期 2002.04.10
申请号 JP20010174355 申请日期 2001.06.08
申请人 SONY CORP 发明人 NOMURA AOSHI;FUKAMI TADASHI;GOTO MASARU;KOIZUMI TAKAYOSHI
分类号 G06F1/04;H03L7/08;H03L7/183;H04J3/06;H04J11/00;H04L7/00;H04L7/033 主分类号 G06F1/04
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