Method and apparatus for partitioning long scan chains in scan based BIST architecture

摘要

A technique is provided for testing an IC which includes a plurality of flip-flops. The flip-flops are arranged in at least one scan chain. The testing technique of the invention is practiced by selectively partitioning the scan chain into smaller scan chains so that the smaller chains can be simultaneously latched and provide test results. The scan chain is switchable between a partitioned and a non-partitioned configuration, so that either configuration can be selected on demand, thereby allowing both BIST and deterministic testing to be performed efficiently on the same circuit.